View MAX8707ETL_4581786.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max8707 is a multiphase (3-/4-phase), interleaved, fixed-frequency, step-down controller for amd hammer cpu core supplies. interleaved multiphase operation reduces the input ripple current and output voltage ripple while easing component selection and layout placement. the max8707 includes active voltage positioning with adjustable gain and offset, reducing power dissipation and bulk output-capacitance requirements. the max8707 is intended for two different notebook cpu core applications: stepping down the battery directly or stepping down the +5v system supply to create the core voltage. the single-stage conversion method allows these devices to directly step down high-voltage batteries for the highest possible efficien- cy. alternatively, 2-stage conversion (stepping down the +5v system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. the max8707 features dedicated differential current- sense inputs for each phase and includes a fifth pair of current-sense inputs to provide an accurate voltage- positioning slope and average current-limit protection using a single current-sense resistor. the max8707 also has two dedicated inputs that provide differential remote voltage sensing. the max8707 provides an analog input for setting the suspend voltage and a slew-rate controller for transi- tions between vid codes or the suspend voltage. the controllers reduce the transition slew rate during startup and shutdown, providing soft-start with minimal input surge current and damped soft-shutdown without nega- tive output undershoot. the max8707 includes output fault protection?ndervoltage, nonlatched overvoltage, and thermal overload?nd an independent voltage- regulator power-ok (vrok) output. the max8707 has a selectable switching frequency, allowing 200khz, 300khz, or 600khz per-phase opera- tion. the max8707 is available in the low-profile, 40-pin, 6mm x 6mm thin qfn package. refer to the max8702/ max8703 for compatible drivers. features 3-/4-phase interleaved fixed-frequency controller ?.75% v out accuracy over line, load, and temperature 5-bit on-board digital-to-analog converter (dac)?.80v to 1.55v adjustable suspend voltage input active voltage positioning with adjustable gain and offset accurate lossless current balance accurate droop and current limit remote output and ground sense output slew-rate control power-good window comparator selectable 200khz/300khz/600khz switching frequency output overvoltage and undervoltage protection thermal fault protection 2v ?.7% reference output soft-startup and shutdown max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ________________________________________________________________ maxim integrated products 1 ordering information 19-3360; rev 0; 8/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX8707ETL -40 c to +85 c 40 thin qfn 6mm x 6mm applications amd hammer desknote computers multiphase cpu core supplies voltage-positioned step-down converters notebook/desktop computers servers pin configuration appears at end of data sheet.
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ..............................................................-0.3v to +6v d0 d4 to gnd..........................................................-0.3v to +6v skip, sus, vrok, ilim(ave) to gnd......................-0.3v to +6v susv, ofs, osc to gnd.........................................-0.3v to +6v csp_, csn_, crsp, crsn to gnd .........................-0.3v to +6v vps, fbs, ccv, ref to gnd .....................-0.3v to (v cc + 0.3v) ilim(pk), trc, time to gnd .....................-0.3v to (v cc + 0.3v) pwm_, drskp to pgnd ............................-0.3v to (v cc + 0.3v) pgnd, gnds to gnd ...........................................-0.3v to +0.3v shdn to gnd (note 1)...........................................-0.3v to +14v ref short-circuit duration .........................................continuous continuous power dissipation (t a = +70 c) 40-pin 6mm x 6mm thin qfn (derate 26.3mw/ c above +70 c) ................................2.105w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units pwm controller input voltage range v cc 4.5 5.5 v dac codes from 1.10v to 1.55v -0.75 +0.75 dac codes from 0.80v to 1.075v -2.0 +2.0 % dc output voltage accuracy v out includes load- regulation error (vps = fbs) sus = v cc -20 +20 mv susv input range v susv 0.4 2.0 v susv input-bias current i susv v susv = 0.4v to 2v -0.1 +0.1 a negative offsets 0 0.8 ofs input range v ofs positive offsets 1.2 2.0 v ? v out / ? v ofs , ? v ofs = v ofs , v ofs = 0 to 0.8v -0.131 -0.125 -0.118 ofs gain a ofs ? v out / ? v ofs , ? v ofs = v ofs -v ref , v ofs = 1.2v to 2v -0.131 -0.125 -0.118 v/v ofs input-bias current i ofs v ofs = 0 to 2v -0.1 +0.1 a gnds input range v gnds -200 +200 mv gnds gain a gnds ? v out / ? v gnds , -200mv v gnds +200mv 0.95 1.00 1.05 v/v gnds input-bias current i gnds -2 +2 a fbs input-bias current i fbs crsp = crsn, csp_ = csn_ -10 +10 a osc = gnd 180 200 220 osc = ref 270 300 330 switching frequency accuracy (per phase) f sw osc = v cc 540 600 660 khz note 1: shdn can be forced to 12v for debugging prototype boards using the no-fault test mode, which disables fault protection.
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units r time = 143k ? (6.25mv/s) -10 +10 r time = 47k ? (19mv/s) to 392k ? (2.28mv/s) -15 +15 time slew-rate accuracy startup and shutdown, r time = 47k ? (4.75mv/s) to 392k ? (0.57mv/s) -20 +20 % bias and reference quiescent supply current (v cc ) i cc measured at v cc , vps and fbs forced above the regulation points 712ma shutdown supply current (v cc ) i cc ( shdn ) measured at v cc , shdn = gnd 0.05 10 a reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.986 2.000 2.014 v i ref = 0 to 500a -2 -0.2 reference load regulation ? v ref i ref = -100a to 0 0.21 6.2 mv fault protection pwm (skip = gnd) or skip mode when v out v trip 150 200 250 mv measured at vps with respect to unloaded output voltage, rising edge, 8mv hysteresis skip = v cc and v out > v trip 1.70 1.75 1.80 output overvoltage-protection threshold v ovp minimum ovp level 1.1 v output overvoltage propagation delay t ovp vps forced 25mv above trip threshold 10 s output undervoltage-protection threshold v uvp measured at vps with respect to 70% of the unloaded nominal output voltage -30 +30 mv output undervoltage propagation delay t uvp vps forced 25mv below trip threshold 10 s vrok transition blanking time t blank measured from the time when vps reaches the target voltage, slew rate set by r time (note 2) 20 s undervoltage measured at vps with respect to 87.5% unloaded output voltage, falling edge, 15mv hysteresis -30 +30 vrok threshold overvoltage measured at vps with respect to 112.5% of the unloaded output voltage, rising edge, 15mv hysteresis -30 +30 mv vrok delay t vrok vps forced 25mv outside the vrok trip thresholds 10 s vrok output low voltage i sink = 3ma 0.4 v vrok leakage current high state, vrok forced to 5.5v 1 a
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units v cc undervoltage-lockout threshold v uvlo ( vcc ) rising edge, hysteresis = 20mv, pwm_ disabled below this level 4.10 4.25 4.45 v thermal-shutdown threshold t shdn rising edge hysteresis = 15 c +160 c droop and transient response dc droop amplifier offset -1.5 +1.5 mv dc droop amplifier transconductance (crs sense enabled) g m ( vps ) ? i vps / (n x ? v crs ), v vps = v crsn = 1.2v, v crsp - v crsn = -60mv to +60mv, n = number of phases enabled 194 200 206 s dc droop amplifier transconductance (crs sense disabled) g m ( vps ) ? i vps / ( ? v cs ), v crsp = v cc , v vps = v csn _ = 1.2v, v csp _ v csn _ = -60mv to +60mv 194 200 206 s transient-droop transresistance r trans current-sense gain (a cs = 10 typ) divided by the voltage preamplifier transconductance (g m(trc) = 2ms typ) 4.75 5.0 5.25 k ? transient detection threshold measured at vps with respect to steady- state vps regulation voltage; falling edge, 5.5mv hysteresis (typ) -30 -25 -20 mv current limit and balance current-sense input preamplifier offsets csp_ - csn_ -2.0 +2.0 mv ilim(ave) input range (adjustable mode) v ilim ( ave ) v ref - 1.0 v ref - 0.2 v ilim(ave) average current-limit threshold voltage (positive, default) v avelimit crsp - crsn; ilim(ave) = v cc 22 25 28 mv v ilim ( ave ) = v ref - 0.2v 71013 ilim(ave) average current-limit threshold voltage (positive, adjustable) v avelimit crsp - crsn v ilim ( ave ) = v ref - 1.0v 46 50 54 mv ilim(ave) average current-limit threshold voltage (negative) crsp - crsn; ilim(ave) = v cc -30 -25 -20 mv ilim(ave) input current i ilim ( ave ) -0.1 +0.1 a ilim(ave) current-limit default switchover threshold 3 v cc - 1.0 v cc - 0.4 v v pklimit = 30mv 24 30 36 ilim(pk) peak current-limit threshold voltage (positive) v pklimit csp_ - csn_, r ilim(pk) = r trc x 8v / v lim(pk) v pklimit = 50mv 40 50 60 mv ilim(pk) peak current-limit threshold voltage (negative) csp_ - csn_, r ilim(pk) = r trc x 8v / v pklimit , v pklimit = 50mv -60 -50 -40 mv
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = 0 c to +85 c , unless otherwise specified. typical values are at t a = +25 c.) parameter symbol conditions min typ max units ilim(pk) idle current-limit threshold voltage (skip mode) v idle c s p _ - c s n _, v s ki p 1.2v , r i li m ( p k ) = r t rc x 8v / v p kl im it , v p kl im it = 50m v 258mv csp_, crsp -0.2 +0.2 current-sense input current csn_, crsn -1.0 +1.0 a current-sense common-mode input range crsp, crsn, csp_, csn_ 0 2 v phase disable threshold csp4 3 v cc - 1 v cc - 0.4 v crs sense input disable threshold crsp 3 v cc - 1 v cc - 0.4 v logic and i/o logic input high voltage v ih shdn , sus 2.4 v logic input low voltage v il shdn , sus 0.8 v shdn no-fault threshold to enable no-fault mode 11 13 v d0 d4 logic input high voltage 0.8 v d0 d4 logic input low voltage 0.4 v high (v cc ) v cc - 0.4 medium (ref) 1.8 2.2 osc 3-level input logic levels v osc low (gnd) 0.4 v high 1.2 skip input logic levels v skip low (gnd) 0.8 v logic input current shdn , skip, sus, osc, d0 d4 = 0 to 5v -1 +1 a logic output high voltage v oh pwm_, drskp ; i source = 3ma v cc - 0.4 v logic output low voltage v ol pwm_, drskp ; i sink = 3ma 0.4 v
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 6 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = -40 c to +85 c , unless otherwise specified.) (note 3) parameter symbol conditions min max units pwm controller input voltage range v cc 4.5 5.5 v dac codes from 1.10v to 1.55v -1.0 +1.0 dac codes from 0.80v to 1.075v -3.0 +3.0 % dc output voltage accuracy v out includes load- regulation error (vps = fbs) sus = v cc -25 +25 mv susv input range v susv 0.4 2.0 v negative offsets 0 0.8 ofs input range v ofs positive offsets 1.2 2.0 v ? v out / ? v ofs ; ? v ofs = v ofs, v ofs = 0 to 0.8v -0.131 -0.118 ofs gain a ofs ? v out / ? v ofs ; ? v ofs = v ofs - v ref, v ofs = 1.2v to 2v -0.131 -0.118 v/v gnds input range v gnds -200 +200 mv gnds gain a gnds ? v out / ? v gnds , -200mv v gnds +200mv 0.95 1.05 v/v osc = gnd 180 220 osc = ref 270 330 switching frequency accuracy (per phase) f sw osc = v cc 540 660 khz r time = 143k ? (6.25mv/s) -10 +10 r time = 47k ? (19mv/s) to 392k ? (2.28mv/s) -15 +15 time slew-rate accuracy startup and shutdown, r time = 47k ? (4.75mv/s) to 392k ? (0.57mv/s) -20 +20 % bias and reference quiescent supply current (v cc )i cc measured at v cc , vps and fbs forced above the regulation points 12 ma shutdown supply current (v cc ) i cc ( shdn ) measured at v cc , shdn = gnd 10 a reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.98 2.02 v i ref = 0 to 500a -2 mv reference load regulation ? v ref i ref = -100a to 0 6.2 mv fault protection pwm (skip = gnd) or skip mode when v out v trip 150 250 mv output overvoltage-protection threshold v ovp measured at vps with respect to unloaded output voltage, rising edge, 8mv hysteresis skip = v cc and v out > v trip 1.70 1.80 v
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = -40 c to +85 c , unless otherwise specified.) (note 3) parameter symbol conditions min max units output undervoltage-protection threshold v uvp measured at vps with respect to 70% of the unloaded nominal output voltage -40 +40 mv undervoltage, measured at vps with respect to 87.5% of the unloaded output voltage, falling edge, 15mv hysteresis -40 +40 vrok threshold overvoltage, measured at vps with respect to 112.5% of the unloaded output voltage, rising edge, 15mv hysteresis -40 +40 mv vrok output low voltage i sink = 3ma 0.4 v v cc undervoltage-lockout threshold v uvlo ( vcc ) rising edge, hysteresis = 20mv, pwm_ disabled below this level 4.10 4.45 v droop and transient response dc droop amplifier offset -2 +2 mv dc droop amplifier transconductance (crs sense enabled) g m ( vps ) ? i vps / (n x ? v crs ); v vps = v crsn = 1.2v, v crsp - v crsn = -60mv to +60mv, n = number of phases enabled 190 210 s dc droop amplifier transconductance (crs sense disabled) g m ( vps ) ? i vps / ( ? v cs ), v crsp = v cc , v vps = v csn _ = 1.2v, v csp _ - v csn _ = -60mv to +60mv 190 210 s transient-droop transresistance r trans current-sense gain (a cs = 10 typ) divided by the voltage preamplifier transconductance (g m(trc) = 2ms typ) 4.50 5.25 k ? current limit and balance current-sense input preamplifier offsets csp_ - csn_ -2.5 +2.5 mv ilim(ave) input range (adjustable mode) v ilim ( ave ) v ref - 1.0 v ref - 0.2 v ilim(ave) average current-limit threshold voltage (positive, default) v avelimit crsp - crsn; ilim(ave) = v cc 20 30 mv v ilim ( ave ) = v ref - 0.2v 515 ilim(ave) average current-limit threshold voltage (positive, adjustable) v avelimit crsp - crsn v ilim ( ave ) = v ref - 1.0v 44 56 mv ilim(ave) average current-limit threshold voltage (negative) crsp - crsn; ilim(ave) = v cc -31 -19 mv ilim(ave) current-limit default switchover threshold 3 v cc - 0.4 v
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 8 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1. v cc = v shdn = 5v, osc = ref, v vps = v fbs = v crsn = v crsp = v csp_ = 1.20v, v susv = 0.8v, ofs = sus = gnds = pgnd = skip = gnd, d0 d4 set for 1.20v (d0 d4 = 01110). t a = -40 c to +85 c , unless otherwise specified.) (note 3) parameter symbol conditions min max units v pklimit = 30mv 24 36 ilim(pk) peak current-limit threshold voltage (positive) v pklimit csp_ - csn_, r ilim(pk) = r trc x 8v / v lim(pk) v pklimt = 50mv 40 60 mv ilim(pk) peak current-limit threshold voltage (negative) csp_ - csn_, r ilim(pk) = r trc x 8v / v pklimit , v pklimit = 50mv -60 -40 mv ilim(pk) idle current-limit threshold voltage (skip mode) v idle c s p _ - c s n _, v s ki p 1.2v , r i li m ( p k ) = r t rc x 8v / v p kl im it , v p kl im it = 50m v 28mv csp_, crsp -0.2 +0.2 current-sense input current csn_, crsn -1.0 +1.0 a current-sense common-mode input range crsp, crsn, csp_, csn_ 0 2 v phase disable threshold csp4 3 v cc - 0.4 v crs sense input disable threshold crsp 3 v cc - 0.4 v logic and i/o logic input high voltage v ih shdn , sus 2.4 v logic input low voltage v il shdn , sus 0.8 v d0 d4 logic input high voltage 0.8 v d0 d4 logic input low voltage 0.4 v high (v cc ) v cc - 0.4 medium (ref) 1.8 2.2 osc 3-level input logic levels v osc low (gnd) 0.4 v high 1.2 skip input logic levels v skip low (gnd) 0.8 v logic output high voltage v oh pwm_, drskp ; i source = 3ma v cc - 0.4 v note 2: vrok is blanked during the transitions, when the internal target is being slewed. see the output-voltage transition timing section. vrok is reenabled in t blank (20s) after the transition is completed. note 3: specifications to t a = -40 c are guaranteed by design and are not production tested.
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies _______________________________________________________________________________________ 9 efficiency vs. load current (v out = 1.525v) max8707 toc01 load current (a) efficiency (%) 10 60 70 80 90 100 50 1100 v in = 8v v in = 12v v in = 20v efficiency vs. load current (v out = 1.300v) max8707 toc02 load current (a) efficiency (%) 10 60 70 80 90 100 50 1100 v in = 8v v in = 12v v in = 20v efficiency vs. load current (v out = 1.000v) max8707 toc03 load current (a) efficiency (%) 10 60 70 80 90 100 50 1100 v in = 8v v in = 12v v in = 20v typical operating characteristics (circuit of figure 1. v in = 12v, v cc = 5v, sus = skip = gnd, shdn = v cc , v susv = 0.80v, t a = +25 c, unless otherwise specified.) output voltage deviation vs. load current max8707 toc04 load current (a) output voltage (mv) 60 40 20 -100 -80 -60 -40 -20 0 20 -120 080 v out = 1.00v v out = 1.30v v in = 12v single-phase efficiency vs. load current (v out = 0.800v) max8707 toc05 load current (a) efficiency (%) 110 60 70 80 90 100 50 0.1 100 v in = 8v v in = 12v v in = 20v skip = sus = v cc 0 50 100 150 200 0 5 10 15 20 25 no-load supply current vs. input voltage (4-phase forced-pwm mode) max8707 toc06 input voltage (v) supply current (ma) i bias i in skip = v cc 0 2 6 4 8 10 010 5152025 no-load supply current vs. input voltage (1-phase pulse skipping) max8707 toc07 input voltage (v) supply current (ma) skip = gnd i bias i in = 15 a output offset voltage vs. ofs voltage max8707 toc08 ofs voltage (v) output offset voltage (mv) 1.5 1.0 0.5 -100 -50 0 50 100 150 -150 0 2.0 undefined region reference voltage distribution max8707 toc09 reference voltage (v) sample percentage (%) 2.005 2.000 1.995 10 20 30 40 50 0 1.990 2.010 sample size = 100
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 10 ______________________________________________________________________________________ typical operating characteristics (circuit of figure 1. v in = 12v, v cc = 5v, sus = skip = gnd, shdn = v cc , v susv = 0.80v, t a = +25 c, unless otherwise specified.) output offset voltage distribution max8707 toc10 output offset voltage (mv) sample percentage (%) 1 -1 -3 10 20 30 40 50 0 -5 5 3 sample size = 100 1.550v 0.800v vps transconductance distribution max8707 toc11 transconductance ( s) sample percentage (%) 203 201 199 197 10 20 30 40 50 60 70 0 195 205 sample size = 100 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 25 current-sense voltage difference vs. load current max8707 toc12 load current (a) current-sense difference (mv) startup waveform (no load) max8707 toc13 a. shdn, 5v/div b. drskp, 10v/div c. ref, 2v/div d. out, 1v/div e. vrok, 10v/div f. dl1, 10v/div g. inductor current (i l1 ), 10a/div 200 s/div 0 0 3.3v a b c d e f g 0 0 5v 2v 1v startup waveform (20a load) max8707 toc14 a. shdn, 5v/div b. drskp, 10v/div c. ref, 2v/div d. out, 1v/div e. vrok, 10v/div f. dl1, 10v/div g. inductor current (i l1 ), 10a/div 200 s/div 0 0 3.3v a b c d e f g 0 0 5v 2v 1v shutdown waveform (no load) max8707 toc15 a. shdn, 5v/div b vrok, 10v/div c. out, 1v/div d. dl1, 10v/div e. inductor current (i l1 ), 10a/div 200 s/div 0 0 3.3v a b c d e 0 0 5v 1.3v
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 11 typical operating characteristics (continued) (circuit of figure 1. v in = 12v, v cc = 5v, sus = skip = gnd, shdn = v cc , v susv = 0.80v, t a = +25 c, unless otherwise specified.) load transient (v out = 1.30v) max8707 toc16 a. i out = 10a to 65a, 50a/div b. v out , 100mv/div c. lx1, 10v/div d. inductor current (i l1 ), 10a/div 20 s/div 0 0 65a a b c d 10a 1.30v 12v 10a 20a load transient (v out = 1.00v) max8707 toc17 a. i out = 0 to 30a, 50a/div b. v out , 50mv/div c. lx1, 10v/div d. inductor current (i l1 ), 10a/div 20 s/div 0 0 30a a b c d 0 1.00v 12v 10a transient phase repeat max8707 toc18 a. i out = 0 to 70a, 100a/div b. v out , 100mv/div c. lx1, 10v/div d. inductor current (i l1 ), 10a/div 2 s/div 0 0 70a a b c d 0a 1.30v 20v 20a 10a v in = 20v deep-sleep transition max8707 toc19 a. dpslp, 5v/div b. ofs, 200mv/div c. v out , 25mv/div d. inductor current (i l1 ), 10a/div e. inductor current (i l3 ), 10a/div 20 s/div 0 3.3v a b c d e 0 0.2v 1.300v 1.275v 5a 5a i out = 20a suspend exit transition max8707 toc20 a. sus, 5v/div b. v out , 500mv/div c. drskp, 5v/div d. inductor current (i l1 ), 10a/div e. inductor current (i l3 ), 10a/div 20 s/div 0 3.3v a b c d e 0 1.30v 0.80v 5v suspend transition (skip = sus) max8707 toc21 a. sus, 5v/div b. v out , 500mv/div c. drskp, 5v/div d. inductor current (i l1 ), 10a/div e. inductor current (i l3 ), 10a/div 200 s/div 0 3.3v a b c d e 0 1.30v 0.80v 5v
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 12 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1. v in = 12v, v cc = 5v, sus = skip = gnd, shdn = v cc , v susv = 0.80v, t a = +25 c, unless otherwise specified.) suspend transition (skip = sus) max8707 toc22 a. sus, 5v/div b. v out , 500mv/div c. drskp, 5v/div d. inductor current (i l1 ), 10a/div e. inductor current (i l3 ), 10a/div 100 s/div 0 3.3v a b c d e 0 1.30v 0.80v 5v suspend transition (skip = gnd) max8707 toc23 a. sus, 5v/div b. v out , 500mv/div c. drskp, 5v/div d. inductor current (i l1 ), 10a/div e. inductor current (i l3 ), 10a/div 40 s/div 0 3.3v a b c d e 0 1.30v 0.80v 5v d1 (25mv) vid transition max8707 toc24 a. d1, 5v/div b. v out , 25mv/div c. inductor current (i l1 ), 10a/div d. inductor current (i l3 ), 10a/div 20 s/div 0 0 3.3v a b c d 0 1.30v 1.275v d3 (200mv) vid transition max8707 toc25 a. d3, 5v/div b. v out , 200mv/div c. inductor current (i l1 ), 10a/div d. inductor current (i l3 ), 10a/div 20 s/div 0 0 3.3v a b c d 0 1.30v 1.10v
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 13 pin description pin name function 1d2 low-voltage vid dac code input. the d0 d4 inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. in normal mode (table 4, sus = gnd), the output voltage is set by the vid code indicated by the logic-level voltages on d0 d4. in suspend mode (sus = high), the output voltage tracks the voltage at susv. 2 d3 low-voltage vid dac code input 3 d4 low-voltage vid dac code input (msb) 4 n.c. no connect. leave open. pin internally connected. 5 skip pulse-skipping indicator input. when pulse skipping, the controller blanks the vrok upper threshold. 3.3v or v cc (high) = 1-phase pulse-skipping operation (phases 2, 3, and 4 disabled) gnd = multiphase forced-pwm operation the controller automatically enters forced-pwm mode during startup, shutdown, and the no-cpu vid mode. 6 shdn shutdown control input. this input cannot withstand the battery voltage. connect to v cc for normal operation. connect to ground to put the ic into its 50na (typ) shutdown state. during the startup and shutdown transitions, the output voltage is ramped at 1/4th the output-voltage slew rate programmed by r time . after completing soft-shutdown, the drivers are disabled drskp and pwm_ are pulled low. forcing shdn to 11v~13v disables both overvoltage-protection and undervoltage-protection circuits, and clears the fault latch. do not connect shdn to >13v. 7 sus suspend control input. when the controller detects a transition on sus, the controller slews the output voltage to the new voltage level determined by susv (sus = high) or d0 d4 (sus = low). the controller blanks vrok during the transition and another 20s after the new target voltage is reached. when sus is high, the offset (ofs) is automatically disabled. 8 susv suspend-mode voltage input. connect to the output of a resistive voltage-divider from ref to gnd to provide an analog voltage between 0.4v to 2v. the output voltage is set by the voltage at susv when sus is high. 9 ilim(ave) average current-limit threshold adjustment. the controller uses the accurate crsp-to-crsn current- sense voltage to limit the average current per phase. when the average current-limit threshold is exceeded, the controller internally reduces the peak inductor current-limit threshold (ilim(pk)) at 2% of i pklimit per s until the average current remains within the programmed limits. when the accurate current sensing is disabled (crsp = v cc ), the average current-limit circuit is disabled and i lim(ave) should be connected to v cc . the average current-limit threshold defaults to 25mv if ilim(ave) is connected to v cc . in adjustable mode, the average current-limit threshold voltage is precisely 1/20th the voltage difference between ilim(ave) and the reference: (v ref - v ilim(ave) ) / 20 for a range of 1.0v (v ref - 1v) to 1.8v (v ref - 0.2v). the logic threshold for switchover to the 25mv default value is approximately v cc - 1v. 10 ofs adjustable offset voltage input. for 0 < v ofs < 0.8v, 1/8th the voltage at ofs is subtracted from the output. for 1.2v < v ofs < 2.0v, 1/8th the difference between ref and ofs is added to the output. voltages in the range of 0.8v < v ofs < 1.2v are undefined. the controller disables the offset amplifier during suspend mode (sus = high).
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 14 ______________________________________________________________________________________ pin description (continued) pin name function 11 osc oscillator select input. osc is a 3-level logic input for selecting the per-phase switching frequency. connect to gnd for 200khz, connect to ref for 300khz, or connect to v cc for 600khz per phase. 12 gnds ground remote-sense input. connect gnds directly to the cpu ground-sense pin. gnds internally connects to an amplifier that adjusts the output voltage, compensating for voltage drops from the regulator ground to the load ground. 13 time slew-rate adjustment pin. connect a resistor from time to gnd to set the internal slew rate. a 47k ? to 392k ? corresponds to slew rates of 19mv/s to 2.28mv/s, respectively, for all suspend voltage transitions. where dv target / dt = 6.25mv/s 143k ? / r time is the slew rate. for soft-start and shutdown, the controller automatically reduces the slew rate by 1/4th. for all dynamic vid transitions, the rate at which the vid inputs (d0 d4) are clocked sets the slew rate, as long as it is less than the dv/dt set by r time . 14 ilim(pk) peak inductor current-limit threshold adjustment (cycle-by-cycle current limit). if the voltage across the current-sense inputs (csp to csn) exceeds the peak current-limit threshold, the controller immediately terminates the respective phase s on-time. connect a resistor r ilim(pk) from ilim(pk) to gnd to set the cycle-by-cycle peak current-limit threshold: where r cs is the resistance value of the current-sense element (inductors dcr or current-sense resistor), r trc is the resistance between trc and ref, and i pklimit is the desired peak current limit (per phase). 15 ccv voltage integrator capacitor connection. connect a 470pf x (4 / ph ) or greater capacitor from ccv to analog ground (gnd) to set the integration time constant. 16 trc transient-voltage preamplifier output. connect a resistor (r trc ) between trc and ref to set the transient droop based on the voltage-positioning requirements. trc does not affect the dc steady-state droop. choose r trc based on the equation: as defined in the design procedure (page 33). if voltage positioning is not required, r trc is determined by the stability requirements. trc is high impedance in shutdown. t vv dv dt tran sus new old target () || / = ? r vr ir ilim pk trc pklimit cs () = 8 ra rr r trc cs trans cs ph droop ac = ? ? ? ? ? ? ()
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 15 pin description (continued) pin name function 17 ref 2.0v reference output. bypass to gnd with a 0.22f to 1f (max) ceramic capacitor. the reference can source 500a for external loads. loading ref degrades output-voltage accuracy according to the ref load-regulation error. 18 vrok open-drain power-good output. after power-up, vrok remains high impedance as long as the output voltage remains in regulation. the controller blanks vrok (high impedance) whenever the slew-rate control is active (output-voltage transitions). vrok is forced low during startup and shutdown. in pulse- skipping mode (skip = high), the upper vrok threshold is disabled. 19 gnd analog ground. connect the max8707 s exposed pad to analog ground. 20 pgnd power ground. ground connection for the driver control outputs (pwm_) and driver skip output ( drskp ). 21 v cc analog supply-voltage input. connect v cc to the system supply voltage (4.5v to 5.5v) with a series 10 ? resistor. bypass to analog gnd with a 1f or greater ceramic capacitor, as close to the ic as possible. 22 pwm1 pwm driver control output for phase 1. logic low in shutdown. 23 pwm2 pwm driver control output for phase 2. logic low in shutdown. 24 pwm3 pwm driver control output for phase 3. logic low in shutdown. 25 pwm4 pwm driver control output for phase 4. logic low when disabled (csp4 = v cc ) and in shutdown. 26 drskp d r i ver s ki p c ontr ol outp ut. p ush/p ul l l og i c outp ut that contr ol s the op er ati ng m od e of the ski p - m od e d r i ver ic s. drskp sw i ng s fr om v c c to p gn d . when drskp i s hi g h, the d r i ver ic s op er ate i n for ced - p wm m od e. when drskp i s l ow , the d r i ver ic s enab l e thei r zer o- cr ossi ng com p ar ator s and op er ate i n p ul se- ski p p i ng m od e. 27 fbs remote feedback sense input. connect fbs to the cpu output sense point. to minimize output-voltage errors due to any resistance in series with the fbs input, the controller generates an fbs input bias current equal in magnitude and opposite in polarity to the vps output current. fbs is high impedance in shutdown. 28 vps voltage-positioning transconductance-amplifier output. connect a resistor r vps between vps and fbs to set the dc steady-state droop (load line) based on the required voltage-positioning slope (see the voltage-positioning amplifier section). r vps = r droop / (r sense x g m(vps) ) where r droop is the desired dc voltage-positioning slope, r sense is the current-sense resistor, and g m(vps) = 200s. r sense is the accurate sense resistor used to generate current-sense voltage (crsp, crsn). when crsp is connected to v cc , the input to the transconductance amplifier is the sum of the current-sense voltage (csp_, csn_) inputs. when the inductors dc resistances (r dcr ) are used as the current-sense elements (for lossless sensing), r vps should include an ntc thermistor to minimize the temperature dependence of the voltage-positioning slope. to disable voltage positioning, short vps to fbs. vps is high impedance in shutdown. 29 crsn negative current-sense resistor input. crsn is the negative differential input used for accurate sensing of the phase 1 inductor current. connect a current-sense resistor between crsp and crsn for accurate voltage positioning and current limit. float crsn when not used (crsp pulled up to v cc ).
max8707 detailed description +5v bias supply (v cc ) the max8707 requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebook s 95%-efficient, +5v system supply. keeping the bias supply external to the controller improves efficiency and eliminates the cost associated with the +5v linear regulator that would otherwise be needed to supply the pwm circuit and gate drivers. if stand-alone capability is needed, the +5v bias supply can be generated with an external linear regulator. the +5v bias supply must provide v cc (pwm con- troller) and v drv (fet gate-drive power), so the maxi- mum current drawn is: i bias = i cc + i drive where i cc is provided in the electrical characteristics table and i drive is the driver s supply current dominat- ed by f sw x q g (per phase) as defined in the driver s data sheet. if the +5v bias supply is powered up prior to the battery supply, the enable signal ( shdn going from low to high) must be delayed until the battery volt- age is present to ensure startup. multiphase, fixed-frequency controller for amd hammer cpu core power supplies 16 ______________________________________________________________________________________ pin description (continued) pin name function 30 crsp positive current-sense resistor input. crsp is the positive differential input used for accurate sensing of the phase 1 inductor current. connect a current-sense resistor between crsp and crsn. if current-sense resistors are used on all phases (csp_, csn_), this additional current-sense (crsp, crsn) feature can be disabled by connecting crsp to v cc and floating crsn. 31 csp1 positive current-sense input for phase 1. this input should be connected to the positive terminal of the current-sense resistor or of the dcr sensing filtering capacitor, depending on the current-sense method implemented. 32 csn1 negative current-sense input for phase 1 33 csn2 negative current-sense input for phase 2 34 csp2 positive current-sense input for phase 2. this input should be connected to the positive terminal of the current-sense resistor or of the dcr sensing filtering capacitor, depending on the current-sense method implemented. 35 csp3 positive current-sense input for phase 3. this input should be connected to the positive terminal of the current-sense resistor or of the dcr sensing filtering capacitor, depending on the current-sense method implemented. 36 csn3 negative current-sense input for phase 3 37 csn4 negative current-sense input for phase 4 38 csp4 positive current-sense input for phase 4. this input should be connected to the positive terminal of the current-sense resistor or of the dcr sensing filtering capacitor, depending on the current-sense method implemented. connect csp4 to v cc for fixed 3-phase operation. 39 d0 low-voltage vid-dac code inputs. the d0 d4 inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. in normal mode (table 4, sus = low), the output voltage is set by the d0 d4 vid-dac inputs. in suspend mode (sus = high), the output voltage tracks the voltage at susv. 40 d1 low-voltage vid-dac code inputs
switching frequency (osc) osc is a 3-level logic input used to set the per-phase switching frequency. connect osc directly to gnd, ref, or v cc for 200khz, 300khz, and 600khz opera- tion, respectively. high-frequency (600khz, osc = v cc ) operation optimizes the application for the small- est component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra- portable devices where the load currents are lower. low-frequency (200khz, osc = gnd) operation offers the best overall efficiency at the expense of component size and board space. interleaved multiphase operation the max8707 interleaves all the active phases result- ing in out-of-phase operation that minimizes the input and output filtering requirements, reduces electromag- netic interference (emi), and improves efficiency. the multiphase controller shares the current between multiple phases that operate 90 out-of-phase (4-phase opera- tion) or 120 out-of-phase (3-phase operation). the high- side mosfets do not turn on simultaneously during normal operation. the instantaneous input current is effectively reduced by the number of active phases, resulting in reduced input voltage ripple, esr power loss, and rms ripple current (see the input-capacitor selection section). therefore, the controller achieves high performance while minimizing the component count which reduces cost, saves board space, and lowers component power requirements making the max8707 ideal for high-power, cost-sensitive applications. transient phase repeat when a transient occurs, the response time of the con- troller depends on its ability to quickly respond to the output-voltage deviation and slew the inductor current to the new current level. multiphase, fixed-frequency controllers typically respond only to the clock edge, resulting in a delayed response from the actual tran- sient event. to eliminate this delay time, the max8707 includes transient phase repeat, which allows the con- troller to immediately respond when heavy load tran- sients are detected. if the controller detects that the output voltage has dropped by 25mv, the transient detection comparator immediately retriggers the phase that completed its on-time last. the controller triggers the subsequent phases as normal on the appropriate oscillator edges. this effectively triggers a phase a full cycle early, increasing the total inductor-current slew rate and providing an immediate transient response. feedback-adjustment amplifiers voltage-positioning amplifier (steady-state droop) the multiphase controllers include a transconductance amplifier for adding gain to the voltage-positioning sense path. the current-sense inputs differentially sense the voltage across either a single current-sense resistor (crs sensing enabled) or the inductor s dcr (crs sensing disabled). the vps amplifier s input is generated by sensing either a single phase (crs sens- ing) and multiplying by the number of active phases, or by summing the current-sense (cs_) inputs of all active phases (crsp = v cc ). the transconductance amplifi- er s output connects to the regulator s voltage-posi- tioned feedback input (vps), so the resistance between vps and the output voltage-sense point (fbs) deter- mines the voltage-positioning gain: v out = v target - r vps i vps where the target voltage (v target ) is defined in the nominal output-voltage selection section, and the transconductance amplifier s output current (i vps ) is determined by the current-sense voltage and the num- ber of active phases ( ph ): i vps = ph (v crsp - v crsn ) g m(vps) when crs sensing is enabled, or: i vps = (v csp_ - v csn_ ) g m(vps) when crs sensing is disabled (crsp = v cc ). where g m(vps) is typically 200s as defined in the electrical characteristics table . to avoid output-voltage errors caused by the vps current flowing through para- sitic trace resistance or feedback fliter resistance, a second transconductance amplifier generates an equal and opposite current on the fbs input. disable voltage positioning by shorting vps directly to fbs. max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 17
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 18 ______________________________________________________________________________________ vrok v cc fbs gnd ref ilim(ave) ilim(pk) ofs trc sus susv ref pwm1 csn1 csp1 pwm2 pwm3 pwm4 crsn crsp osc d0 d1 d2 d3 d4 vid inputs drskp lx1 dh1 dl1 lx2 dh2 dl2 bst2 bst1 pgnd drhot pwm1 skip pwm2 tset v cc agnd shdn csn2 csp2 csn3 csp3 lx1 dh1 dl1 lx2 dh2 dl2 bst2 bst1 pgnd pwm1 skip pwm2 tset v cc agnd csn4 csp4 r ilimave1 49.9k ? r ilimave2 150k ? r trc 2.0k ? r ilim(pk) 200k ? on skip off pwm r ofs1 182k ? r ofs2 20k ? 3-level pin r susv2 81k ? r susv1 120k ? dprslpvr vps ccv time gnds c gnds 1000pf c fbs 1000pf r fbs 10 ? pgnd r vrok 100k ? 5v 5v bias 5v bias r crsense 1.0m ? l1 l2 l3 l4 (vron) drhot shdn cpu remote-sense connections c in c in 8v to 20v pwr input output (cpu core supply) 8v to 20v pwr input vron vron v dd v dd c ref 0.22 f r vps 6.49k ? r gnds 10 ? c csn4 4700pf c cs4 0.22 f c csn3 4700pf c cs3 0.22 f c ccv 1000pf r time 143k ? r csp3 1.5k ? r csp4 1.5k ? n h3 n h4 n l3 n l4 r vcc2 10 ? c vcc2 1.0 f r tset2 c vdd2 4.7 f max8702 c csn2 4700pf c cs2 0.22 f r csp3 1.5k ? c crs 1000pf c csn1 4700pf r crsn 100 ? r crsp 100 ? r csp1 1.5k ? c cs1 0.22 f c vcc 1.0 f r vcc 10 ? n h1 n h2 n l1 n l2 r vcc1 10 ? r tset1 c vcc1 1.0 f r drhot 100k ? c vdd1 4.7 f max8707 shdn skip max8702 figure 1. standard max8707 amd hammer application circuit
transient-droop amplifier the max8707 controller includes a transient-droop transconductance amplifier to handle the instantaneous load transients typical of cpu applications. the tran- sient-droop amplifier sets the correct voltage-positioning slope during a load transient, complimenting the slower steady-state voltage-positioning amplifier. the current- sense inputs differentially sense the voltage across the csp_ and csn_ current-sense element (inductor s dcr or current-sense resistor). the transconductance amplifi- er s output connects to the regulator s transient-response input (trc), so the resistance between trc and the ref- erence voltage (ref) determines the transient voltage- positioning gain as defined in the multiphase, fixed-frequency design procedure section. if voltage positioning is not required, r droop is defined by the maximum output-voltage sag with the worst-case transient load ( ? v out / ? i out ) and is sub- ject to stability requirements. trc is high impedance in shutdown. differential remote sense the multiphase controllers include differential, remote- sense inputs to eliminate the effects of voltage drops down the pc board traces and through the processor s power pins. the max8707 gnds amplifier adds an offset directly to the target voltage, adjusting the output voltage to coun- teract the voltage drop in the ground path. connect the feedback sense (fbs), voltage-positioning resistor (r vps ), and ground-sense (gnds) inputs directly to the processor s core supply remote- sense outputs. integrator amplifier an integrator amplifier forces the dc average of the vps voltage to equal the target voltage. this transcon- ductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage ( figure 2), allowing accurate dc output-voltage regula- tion regardless of the output ripple voltage. the integra- tor amplifier has the ability to shift the output voltage by 100mv (typ). the differential input voltage range is at least 60mv total, including dc offset and ac ripple. the integration time constant can be set easily with an external compensation capacitor at the ccv pin. use a 470pf x (4 / ph ) or greater ceramic capacitor. the max8707 disables the integrator by connecting the amplifier inputs together at the beginning of all transi- tions done in pulse-skipping mode (skip = high). the integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). when voltage positioning is disabled (vps = fbs), the transient droop must be less than the 80mv minimum adjustment range of the integrator amplifier to guaran- tee proper dc output-voltage accuracy. offset amplifier the multiphase controllers include a fifth amplifier used to add small offsets to the voltage-positioned load line. the offset amplifier sums directly with the target volt- age, making the offset gain independent of the dac code. this amplifier has the ability to offset the output by 100mv. the offset is adjusted using resistive volt- age-dividers at the ofs input. for inputs from 0 to 0.8v, the offset amplifier adds a negative offset to the output that is equal to 1/8th the voltage appearing at the ofs input (v offset = -0.125 x v ofs ). for inputs from 1.2v max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 19 max8707 amd hammer components designation circuit of figure 1 input voltage range 7v to 24v vid output voltage (d4 d0) 1.50v (d4 d0 = 00010) susv suspend voltage (sus = high) 0.80v maximum load current 80a number of phases ( total ) 4 phases (1) max8705 + (2) max8702 inductor (per phase) 0.56h, 1.6m ? panasonic etqp4lr56wfc switching frequency (per phase) 300khz (osc = ref) high-side mosfet (n h , per phase) siliconix (1) si7892dp low-side mosfet (n l , per phase) siliconix (2) si7356dp total input capacitance (c in ) (8) 10f, 25v tdk c3225x7r1e106m taiyo yuden tmk325bj106mn total output capacitance (c out ) (6) 330f, 2.5v, 9m ? sanyo 2r5tpe330m9 current-sense resistor (r sense ) 1.0m ? panasonic erjm1wtj1m0u table 1. component selection for standard multiphase applications
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 20 ______________________________________________________________________________________ figure 2. max8707 functional diagram max8707 r-to-i converter trc g m(vps) g m(trc) crsp crsn ilim(pk) r-to-i converter vps droop ccv load-transient detect comparator tran susv dac target fault (uvp + thermal) vrok pgood and fault detect csn_ csp_ error amp sus uvlo refok run ref gnd v cc ref (2.0v) fault d4 d3 d2 d1 d0 decoder ref trc clamp ilim(ave) current- limit comparator 25mv 160 s ref change a = 10 phase enable detect ea[4:1] pwm_ pgnd 4-phase fixed-freq current-mode pwm logic sus skip drskp run c slew target window comparator change osc oscillator fbs x 4 g m g m gnds ofs time target sus x 4 integrator amp vps 500k ? skip shdn
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 21 manufacturer website bi technologies www.bitechnologies.com central semiconductor www.centralsemi.com coilcraft www.coilcraft.com coiltronics www.coiltronics.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet www.kemet.com panasonic www.panasonic.com sanyo www.secc.co.jp siliconix (vishay) www.vishay.com sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com toko www.tokoam.com table 2. component suppliers shdn sus skip ofs output voltage operating mode gnd x x x gnd low-power shutdown mode. pwm_ outputs are forced low, and the controller is disabled. the supply current drops to 10a (max). v cc gnd gnd gnd or ref d0 d4 (no offset) normal operation. the no-load output voltage is determined by the selected vid dac code (d0 d4, table 4). v cc gnd v cc gnd or ref d0 d4 (no offset) pulse-skipping operation. when skip is pulled high, the max8707 immediately enters pulse-skipping operation allowing automatic pwm/pfm switchover under light loads. the vrok upper threshold is blanked. v cc gnd x 0 to 0.8v or 1.2v to 2.0v d0 d4 (plus offset) deep-sleep mode. the no-load output voltage is determined by the selected vid-dac code (d0 d4, table 4) plus the offset voltage set by ofs. v cc v cc xx susv (no offset) suspend mode/one phase skip. the no-load output voltage is determined by the suspend voltage present on susv, overriding all other active modes of operation. v cc x x x gnd fault mode. the fault latch has been set by either uvp or thermal shutdown. the controller remains in fault mode until v cc power is cycled or shdn toggled. table 3. operating-mode truth table x = don t care
max8707 to 2v, the offset amplifier adds a positive offset to the output that is equal to 1/8th the difference between the reference voltage and the voltage appearing at the ofs input (v offset = 0.125 x (v ref - v ofs )). with this scheme, the controller supports both positive and neg- ative offsets with a single input. the piecewise linear- transfer function is shown in figure 3. the regions of the transfer function below zero, above 2.0v, and between 0.8v and 1.2v are undefined. ofs inputs are disallowed in these regions, and the respective effects on the output are not specified. the controller disables the offset amplifier during sus- pend mode (sus = high). nominal output-voltage selection the nominal no-load output voltage (v target ) is defined by the selected voltage reference (vid dac or susv) plus the offset voltage and remote ground-sense adjust- ment (v gnds ) as defined in the following equation: v target = v dac + v offset + v gnds when sus = gnd where v dac is the selected vid voltage during normal operation (sus = low, table 4), and v offset is the offset voltage defined by the ofs pin ( figure 3). in suspend mode (sus = high), the offset voltage amplifier is disabled and the target voltage tracks the susv input voltage: v target = v susv + v gnds when sus = v cc the max8707 uses a multiplexer that selects from one of three different inputs ( figure 2) the output of the vid dac, the susv suspend voltage, or ground (controller disabled). on startup, the max8707 slews the target volt- age from ground to either the decoded d0 d4 (sus = low) voltage or the susv voltage (sus = high). dac inputs (d0?4) during normal forced-pwm operation (sus = low), the dac programs the output voltage using the d0 d4 inputs. d0 d4 are low-voltage (1.0v) logic inputs, designed to interface directly with the cpu. do not leave d0 d4 unconnected. d0 d4 can be changed while the max8707 is active, initiating a transition to a new output- voltage level. change d0 d4 together, avoiding greater than 50ns skew between bits. otherwise, incorrect dac readings may cause a partial transition to the wrong volt- age level followed by the intended transition to the cor- rect voltage level, lengthening the overall transition time. the available dac codes and resulting output voltages are compatible with the amd hammer ( table 4) specifi- cations. suspend mode when the processor enters low-power suspend mode, the processor sets the regulator to a lower output voltage to reduce power consumption. the max8707 includes a buffered suspend-voltage input (susv) and a digital sus control input. the suspend voltage is adjusted with an external resistive voltage-divider from ref to susv to analog ground. the suspend-voltage adjustment range is from 0.4v to 2.0v (v ref ). when the cpu suspends operation (sus = high), the controller disables the offset amplifier, overrides the 5-bit vid-dac code set by d0 d4, and slews the output volt- age to the target voltage set by the susv voltage. during the transition, the max8707 blanks both vrok thresh- olds until 20s after the slew-rate controller reaches the suspend-mode voltage. once the 20s timer expires, the max8707 (skip pulled low) automatically switches to the 1-phase, pulse-skipping control scheme, forces drskp low, and blanks the upper vrok threshold. output-voltage transition timing the max8707 performs mode transitions in a controlled manner, automatically minimizing input surge currents. this feature allows the circuit designer to achieve nearly multiphase, fixed-frequency controller for amd hammer cpu core power supplies 22 ______________________________________________________________________________________ output offset voltage vs. ofs input voltage ofs voltage (v ofs ) output offset voltage 1.5v 0.5v 1.0v -100mv 0 100mv 200mv -200mv 0 2.0v 0.8v 1.2v undefined region figure 3. output offset voltage vs. ofs input voltage
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 23 d4 d3 d2 d1 d0 output voltage (v) d4 d3 d2 d1 d0 output voltage (v) 0 0 0 0 0 1.550 1 0 0 0 0 1.150 0 0 0 0 1 1.525 1 0 0 0 1 1.125 0 0 0 1 0 1.500 1 0 0 1 0 1.100 0 0 0 1 1 1.475 1 0 0 1 1 1.075 0 0 1 0 0 1.450 1 0 1 0 0 1.050 0 0 1 0 1 1.425 1 0 1 0 1 1.025 0 0 1 1 0 1.400 1 0 1 1 0 1.000 0 0 1 1 1 1.375 1 0 1 1 1 0.975 0 1 0 0 0 1.350 1 1 0 0 0 0.950 0 1 0 0 1 1.325 1 1 0 0 1 0.925 0 1 0 1 0 1.300 1 1 0 1 0 0.900 0 1 0 1 1 1.275 1 1 0 1 1 0.875 0 1 1 0 0 1.250 1 1 1 0 0 0.850 0 1 1 0 1 1.225 1 1 1 0 1 0.825 0 1 1 1 0 1.200 1 1 1 1 0 0.800 0 1 1 1 1 1.175 1 1 1 1 1 no cpu* table 4. amd hammer output-voltage vid dac codes (sus = gnd) * no-cpu mode: the controller enters the no-cpu mode by ramping down the output voltage to 0v with the shutdown slew rate. when exiting the no-cpu mode, the controller ramps the output up to the new vid output voltage using the startup slew rate. in no- cpu mode, the controller remains in standby so vid transitions may be detected. ideal transitions, guaranteeing just-in-time arrival at the new output-voltage level with the lowest possible peak currents for a given output capacitance. at the beginning of an output-voltage transition, the max8707 blanks both vrok thresholds, preventing the vrok open-drain output from changing states during the transition. the controller enables the lower vrok threshold approximately 20s after the slew-rate con- troller reaches the target output voltage, but the upper vrok threshold is enabled only if the controller remains in forced-pwm operation. if the controller enters pulse- skipping operation, the upper vrok threshold remains blanked. the slew-rate (set by resistor r time ) must be set fast enough to ensure that the transition can be completed within the maximum allotted time. when transitions occur in pulse-skipping mode, the max8707 sets ovp to 1.75v and disables the integrator at the beginning of all transitions. ovp remains at 1.75v and the integrator remains disabled until 20s after the transition is completed (internal target settles) and the output is in regulation (an error-comparator edge is detected). the max8707 automatically controls the current to the minimum level required to complete the transition in the calculated time. the slew-rate controller uses an inter- nal capacitor and current source programmed by r time to transition the output voltage. the total transi- tion time depends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accura- cy). the slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit set by ilim(ave) and ilim(pk). for voltage transitions into and out of suspend mode, the transition time (t tran ) is given by: where dv target / dt = 6.25mv/s 143k ? / r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see time slew-rate accuracy in the electrical characteristics for t slew lim- its. for soft-start and shutdown, the controller automati- cally reduces the slew rate by 1/4th: t vv dv dt tran sus new old target () || / = -
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 24 ______________________________________________________________________________________ for all dynamic vid transitions, the rate at which the vid inputs (d0 d4) are clocked sets the slew rate, with a maximum slew-rate limit set by the r time value. the practical range of r time is 47k ? to 392k ? correspond- ing to slew rates of 19mv/s to 2.28mv/s, respectively. the output voltage tracks the slewed target voltage, making the transitions relatively smooth. the average inductor current per phase required to make an output-voltage transition is: where dv target / dt is the required slew rate, c out is the total output capacitance, and ph is the number of active phases. suspend transition (forced-pwm operation selected) when the max8707 enters suspend mode while config- ured for forced-pwm operation (skip pulled low), the controller ramps the output voltage down to the pro- grammed susv voltage at the slew rate determined by r time . the controller blanks vrok (forced high imped- ance) until 20s after the transition is completed internal target voltage equals the susv voltage. after this blank- ing time expires, the controller automatically shuts down phases 2, 3, and 4 ( drskp pulled low), and enters sin- gle-phase, pulse-skipping operation. vrok monitors only the lower threshold in skip mode. when exiting suspend mode (sus pulled low), the max8707 immediately activates all enabled phases ( drskp driven high) so the output voltage may be ramped up at the slew rate set by r time . the controller blanks vrok (forced high impedance) until 20s after the transition is completed internal target voltage equals the selected vid-dac voltage. suspend transition (pulse-skipping operation selected) if the max8707 is configured for pulse-skipping opera- tion (skip = high) when sus goes high, the max8707 immediately disables phases 2, 3, and 4 ( drskp pulled low) and enters pulse-skipping operation ( figure 5). the output drops at a rate determined by the load and the output capacitance. the internal target still ramps as before, and vrok remains high impedance until the new target is reached plus an extra 20s. after this time expires, vrok monitors only the lower threshold. when exiting deeper sleep (sus pulled low), the max8707 starts to slew the internal target up towards the new target. the controller remains in skip mode while the output voltage is higher than the internal tar- get. as the internal target approaches the output volt- age, the max8707 activates all enabled phases ( drskp driven high) so the output voltage may be ramped up at the slew rate set by r time . the controller blanks vrok (forced high impedance) until 20s after the transition is completed. forced-pwm operation (normal mode) during soft-start, soft-shutdown, and normal operation when the cpu is actively running (skip = low, table 5) the max8707 operates with a low-noise, forced-pwm con- trol scheme. forced-pwm operation forces drskp high, instructing the drivers to disable their zero-crossing com- parators and force the low-side gate-drive waveforms to constantly be the complement of the high-side gate-drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load +5v bias supply current remains between 10ma to 200ma per phase, depending on the external mosfets and switching frequency. to maintain high efficiency under light-load conditions, the controller switches to a low- power pulse-skipping control scheme after entering sus- pend mode. light-load pulse-skipping operation the max8707 includes a light-load operating-mode con- trol input (skip) used to disable extra phases and enable/disable the driver s zero-crossing comparator. when the driver s zero-crossing comparators are enabled ( drskp pulled low), the controller forces pwm_ low for the disabled phases so the driver pulls dl_ low when its current-sense inputs detect zero inductor current. this keeps the inductor from discharging the output capaci- tors and forces the controller to skip pulses under light- load conditions to avoid overcharging the output. when the zero-crossing comparators are disabled, each con- troller maintains pwm operation under light-load condi- tions (forced pwm). after the max8707 enters suspend mode while config- ured for forced-pwm operation (skip pulled low), the controller automatically switches to the pulse-skipping control scheme 20s after the target voltage reaches the programmed susv voltage. when pulse-skipping operation is enabled, the con- troller terminates the on-time when the output voltage exceeds the feedback threshold and when the current- i c dv dt l out ph target ? (/) tt v dv dt tran start tran shdn target target () () / == 4
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 25 sus vrok internal pwm control drskp forced-pwm auto 1-phase skip pwm1 pwm2 pwm3 pwm4 note: ovp constantly tracks the internal target, and the integrator (ccv) is constantly enabled. cpu core voltage susv vid forced-pwm high-z low threshold only high-z t blank 20 s typ t blank 20 s typ figure 4. suspend transition in forced-pwm mode (skip = low) skip = sus vrok internal pwm control drskp 1-phase skip forced pwm pwm1 pwm2 pwm3 pwm4 ovp/ccv cpu core voltage susv vid t blank 20 s t blank 20 s actual v out target ovp = 1.8v integrator disabled ovp tracks internal target integrator enabled low vrok threshold only high-z high-z figure 5. suspend transition in pulse-skipping operation (skip = sus)
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 26 ______________________________________________________________________________________ skip (input) sus (input) mode drskp (output) operation low (gnd) multiphase forced-pwm high (v dd ) the controller operates with a constant switching frequency, providing low-noise forced-pwm operation. the controller disables the zero-crossing comparators, forcing the low-side gate-drive waveform to constantly be the complement of the high-side gate-drive waveform. low (gnd) high (3.3v or v cc ) 1-phase pulse skipping low (pgnd) the controller automatically switches to pulse-skipping operation 20s after the target voltage reaches the susv voltage. pulse-skipping operation forces the controller into pfm operation under light loads. phase 1 remains active while the other three phases are disabled pwm2, pwm3, and pwm4 pulled low. high (>1.2v) don t care 1-phase pulse skipping low (pgnd) pulse-skipping operation forces the controller into pfm operation under light loads. phase 1 remains active while the other three phases are disabled pwm2, pwm3, and pwm4 pulled low. table 5. skip settings idle mode is a trademark of maxim integrated products, inc. sense voltage exceeds the idle mode ? current-sense threshold (v idle = 0.1 x v pklimit ). under heavy-load conditions, the continuous inductor current remains above the idle-mode current-sense threshold, so the on-time depends only on the feedback-voltage thresh- old. under light-load conditions, the controller remains above the feedback-voltage threshold, so the on-time duration depends solely on the idle-mode current- sense threshold, which is approximately 10% of the full- load current-limit threshold set by ilim(pk). when the controller enters suspend mode while skip is pulled high, the multiphase controller immediately dis- ables three phases, and only the main phase (pwm1) remains active. when pulse skipping, the controller blanks the upper vrok threshold and the ovp threshold tracks the selected vid dac code. the max8707 auto- matically uses forced-pwm operation during soft-start and soft-shutdown, regardless of the skip configuration. idle-mode current sense threshold the idle-mode current-sense threshold forces a lightly loaded regulator to source a minimum amount of ener- gy with each on-time since the controller cannot termi- nate the on-time until the current-sense voltage exceeds the idle-mode current-sense threshold (v idle = 0.1 x v pklimit ). since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses to avoid overcharging the output. when the clock edge occurs, if the output voltage still exceeds the feedback threshold, the con- troller does not initiate another on-time. this forces the controller to actually regulate the valley of the output voltage ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, the max8707 disables three phases and forces drskp low to instruct the skip-mode drivers to activate their zero-crossing comparators. therefore, an inherent automatic switchover to pfm takes place at light loads ( figure 6), resulting in a highly efficient operating mode. this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor cur- rent s zero crossing. the driver s zero-crossing compara- tor senses the inductor current across the low-side mosfet (refer to the skip-mode driver data sheet). once v lx - v pgnd drops below the zero-crossing threshold, the driver forces dl low. this mechanism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the bound- ary between continuous and discontinuous inductor-cur- rent operation (also known as the critical conduction point). the load-current level at which the pfm/pwm crossover occurs, i load(skip) , is given by: the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that i vvv vf l load skip out in out in sw () = ? () 2
results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductor value. generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). current sense the output current of each phase is sensed differential- ly. each phase of the max8707 has an independent return path for fully differential current-sense. a low off- set voltage and high-gain (10v/v) differential current amplifier at each phase allow low-resistance current- sense resistors to be used to minimize power dissipa- tion. sensing the current at the output of each phase offers advantages, including less noise sensitivity, more accurate current sharing between phases, and the flexi- bility of using either a current-sense resistor or the dc resistance of the output inductor. using the dc resistance (r dcr ) of the output inductor allows higher efficiency. in this configuration, the initial tolerance and temperature coefficient of the inductor s dcr must be accounted for in the output-voltage droop-error budget. this current-sense method uses an rc filtering network to extract the current information from the output inductor ( figure 7). the time constant of the rc network should match the inductor s time constant (l/r dcr ): where c sense is the sense capacitor and r eq is the equivalent sense resistance. to minimize the current- sense error due to the current-sense inputs bias cur- rent (i csp _ and i csn _), choose r eq less than 2k ? and use the above equation to determine the sense capaci- tance (c sense ). choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. temperature compensation is recommended for this current-sense method. when using a current-sense resistor for accurate out- put-voltage positioning (crsp to crsn for the max8707), differential rc-filter circuits should be used to cancel the equivalent series inductance of the cur- rent-sense resistor ( figure 7). similar to inductor dcr- sensing methods, the rc filter s time constant should match the l/r time constant formed by the current- sense resistor s parasitic inductance: where l esl is the equivalent series inductance of the current-sense resistor, r sense is the current-sense resistance value, c sense is the compensation capaci- tor, and r eq is the equivalent compensation resistance. current balance the fixed-frequency, multiphase, current-mode archi- tecture automatically forces the individual phases to remain current balanced. after the oscillator triggers an on-time, the controller does not terminate the on-time until the amplified differential current-sense voltage reaches the integrated threshold voltage (v ref - v trc ). this control scheme regulates the peak inductor cur- rent of each phase, forcing them to remain properly balanced. therefore, the average inductor-current vari- ation depends mainly on the variation in the current- sense element and inductance value. peak/average current limit the max8707 current-limit circuit employs a fast peak inductor current-sensing algorithm. once the current- sense signal (csp to csn) of the active phase exceeds the peak current-limit threshold, the pwm controller ter- minates the on-time. the max8707 also includes a slower average current sense that uses a current-sense resistor between crsp and crsn to accurately limit the inductor current. when this average current-sense threshold is exceeded, the current-limit circuit lowers the peak current-limit threshold, effectively lowering the average inductor current. see the current limit section in the design procedure section. l r rc esl sense eq sense = l r rc dcr eq sense = max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 27 on-time time 0 inductor current t on(skip) = v out v in f sw i idle i load i load(skip) 2 figure 6. pulse-skipping/discontinuous crossover point
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 28 ______________________________________________________________________________________ driver input (v in ) c in d l c out lr sense n h n l controller dh dl pgnd csp_ csn_ pwm pwm_ lx a) output series resistor sensing driver input (v in ) c in d l c out lr dcr n h n l controller dh dl pgnd csp_ csn_ pwm pwm_ lx b) lossless inductor sensing inductor r eq c sense figure 7. current-sense methods power-up sequence (por, uvlo) power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the controller for operation. the v cc undervoltage- lockout (uvlo) circuitry inhibits switching forces drskp high and pulls the pwm_ outputs low until v cc rises above 4.25v. the controller powers up the reference once the system enables the controller v cc above 4.25v and shdn pulled high. with the reference in regulation, the controller begins to slew the output voltage to the target voltage either the output of the vid dac (sus = low) or the susv suspend voltage (sus = high) at 1/4th the slew rate set by r time : where dv target / dt = 6.25mv/s 143k ? / r time is the slew rate. the soft-start circuitry does not use a variable current limit, so full output current is available immediate- ly. vrok becomes high impedance approximately 20s after the max8707 reaches the target voltage. for automatic startup, the battery voltage should be present before v cc . if the controller attempts to bring the output into regulation without the battery voltage present, the fault latch trips. the controller remains shut down until the fault latch is cleared by toggling shdn or cycling the v cc power supply below 1v. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to make valid decisions. to protect the output from over- voltage faults, the controller shuts down immediately forces drskp high and pulls the pwm_ outputs low. shutdown when shdn goes low, the max8707 enters low-power shutdown mode. vrok is pulled low immediately, and the output voltage ramps down at 1/4th the slew rate set by r time : where dv target / dt = 6.25mv/s 143k ? / r time is the slew rate. slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output volt- age excursion that occurs when the controller dis- charges the output quickly by permanently turning on the low-side mosfet (underdamped response). this eliminates the need for the schottky diode normally connected between the output and ground to clamp t v dv dt tran shdn out target () / = 4 t v dv dt tran start target target () / = 4
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 29 forced-pwm forced-pwm vid (d0-d4) v core vrok invalid code invalid code internal pwm control drskp v cc soft-start 1/4 th slew rate set by r time soft-shutdown 1/4 th slew rate set by r time shdn t blank 20s typ t blank 20s typ figure 8. power-up and shutdown sequence timing diagram the negative output-voltage excursion. when the con- troller reaches the 0v target, the drivers are disabled ( drskp driven low and pwm_ outputs pulled low), the reference turns off, and the supply current drops to about 10a (max). when a fault condition output uvlo or thermal shutdown activates the shutdown sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the controller, toggle shdn or cycle v cc power below 1v. fault protection output overvoltage protection (unlatched) the overvoltage-protection (ovp) circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the max8707 continuously monitors the output for an overvoltage fault. the controller detects an ovp fault if the output voltage exceeds the set target voltage by more than 200mv. after entering pulse-skipping opera- tion (skip rising edge), the ovp threshold is set to 1.75v until the output voltage drops below the target voltage for the first time. once the max8707 detects the output is being regulated (v out v target ), the ovp threshold begins tracking the target voltage again. when the ovp circuit detects an overvoltage fault, it immediately enters forced-pwm operation pulling drskp high so the drivers force the low-side gate dri- vers high (dl = v dd ) and pull the high-side gate dri- vers low (dh = lx). the controller does not initiate an on-time pulse until the output voltage drops below the ovp threshold. this action turns on the synchronous- rectifier mosfet with 100% duty and, in turn, rapidly discharges the output filter capacitor and forces the output low. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse blows. overvoltage protection can be disabled through the no- fault test mode (see the no-fault test mode section). output undervoltage protection (latched) the output undervoltage-protection (uvp) function is similar to foldback current limiting, but employs a timer rather than a variable current limit. if the max8707 out- put voltage is under 70% of the nominal value, the con- troller activates the shutdown sequence and sets the fault latch. once the controller ramps down to the 0v setting, it forces the pwm_ driver outputs low. toggle shdn or cycle the v cc power supply below 1v to clear the fault latch and reactivate the controller. uvp can be disabled through the no-fault test mode (see the no-fault test mode section). thermal fault protection (latched) the max8707 features a thermal fault-protection circuit. when the junction temperature rises above +160 c, a
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 30 ______________________________________________________________________________________ thermal sensor sets the fault latch and activates the soft-shutdown sequence. once the controller ramps down to the 0v setting, it forces the pwm_ driver out- puts low. toggle shdn or cycle the v cc power supply below 1v to clear the fault latch and reactivate the con- troller after the junction temperature cools by 15 c. thermal shutdown can be disabled through the no-fault test mode (see the no-fault test mode section). no-fault test mode the latched fault protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. therefore, a no-fault test mode is provided to disable the fault protection over- voltage protection, undervoltage protection, and ther- mal shutdown. additionally, the test mode clears the fault latch if it has been set. the no-fault test mode is entered by forcing 11v to 13v on shdn . multiphase, fixed-frequency design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to con- sider. the peak load current (i load(max) ) determines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selec- tion, inductor saturation rating, and the design of the current-limit circuit. the continuous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other criti- cal heat-contributing components. modern notebook cpus generally exhibit i load = i load(max) x 80%. for multiphase systems, each phase supports a frac- tion of the load, depending on the current balancing. when properly balanced, the load current is evenly dis- tributed among each phase: where ph is the total number of active phases. switching frequency: this choice determines the basic trade-off between size and efficiency. the opti- mal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are pro- portional to frequency and v in 2 . the optimum frequen- cy is also a moving target, due to rapid improvements in mosfet technology that are making higher frequen- cies more practical. inductor operating point: this choice provides trade- offs between size vs. efficiency and transient response vs. output noise. low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical induc- tor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size- reduction benefit. the optimum operating point is usu- ally found between 20% and 50% ripple current. inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: where ph is the total number of phases, and f sw is the switching frequency per phase. find a low-loss inductor with the lowest possible dc resistance that fits in the allotted dimensions. if using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor ripple current ( ? i inductor ) is defined by: ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): i i i peak load max ph inductor = ? ? ? ? ? ? + ? ? ? ? ? ? () ? 2 ? i vvv vf l inductor out in out in sw = ? () l vv f i lir v v ph in out sw load max out in = ? ? ? ? ? ? ? ? ? ? ? ? ? () i i load phase load ph () =
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 31 current limit peak inductor current limit (ilim(pk)) the max8707 overcurrent protection employs a peak current-sensing algorithm that uses either current- sense resistors or the inductor s dcr as the current- sense element (see the current sense section). since the controller limits the peak inductor current, the maxi- mum average load current is less than the peak cur- rent-limit threshold by an amount equal to half the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and input voltage. when combined with the undervoltage-protection cir- cuit, this current-limit method is highly effective. the peak current-limit threshold is set with a single exter- nal resistor between ilim(pk) and analog ground, where the resistor is determined by the following equation: where r sense is the resistance value of the current- sense element (inductors dcr or current-sense resis- tor), r trc is the resistance between trc and ref, and i pklimit is the desired peak current limit (per phase). the peak current-limit-threshold voltage adjustment range is from 20mv to 80mv. the peak current-limit circuit also prevents excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is equivalent to the positive current limit, and tracks the positive current limit when r ilim(pk) or r trc are adjusted. when a phase drops below the negative current limit, the controller acti- vates an on-time pulse at the next clock edge, regard- less of the error-amplifier state, until the inductor current rises above the negative current-limit threshold. average inductor current-limit (ilim(ave)) the max8707 also uses the accurate crsp to crsn cur- rent-sense voltage to limit the average current per phase. when the average current-limit threshold is exceeded, the controller internally reduces the peak inductor cur- rent-limit threshold (ilim(pk)) until the average current remains within the programmed limits. when the accurate current sensing is disabled (crsp = v cc ), the average current-limit circuit is disabled. the average current-limit threshold defaults to 25mv if ilim(ave) is connected to v cc . in adjustable mode, the average current-limit threshold voltage is precisely 1/20th the voltage difference between ilim(ave) and the reference: the logic threshold for switchover to the 25mv default value is approximately v cc - 1v. the average current- limit circuit also prevents against excessive reverse inductor current when v out is sinking current. the neg- ative current-limit threshold is equivalent to the positive current limit, and tracks the positive current limit when v lave is adjusted. output-capacitor selection the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitor s size typi- cally depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: in non-cpu applications, the output capacitor s size often depends on how much esr is needed to maintain an acceptable level of output ripple voltage. the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capaci- tor s esr. when operating multiphase systems out-of- phase, the peak inductor currents of each phase are staggered, resulting in lower output ripple voltage (v ripple ) by reducing the total inductor ripple current. for nonoverlapping, multiphase operation (v in ? ph x v out ), the maximum esr to meet the output-ripple- voltage requirement is: where ph is the total number of active phases, and f sw is the switching frequency per phase. the actual capac- itance value required relates to the physical size need- ed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor selection is usually limited by esr and voltage rating rather than by capacitance value (this is true of polymer types). r vf l vvv v esr in sw in ph out out ripple ? ? ? ? ? ? ? ? ? () () () rr v i esr pcb step load max + ? v vv lave ref ilim ave = ? () 20 r vr ir ilim pk trc pklimit sense () = 8
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 32 ______________________________________________________________________________________ the capacitance value required is determined primarily by the output transient-response requirements. low inductor values allow the inductor current to slew faster, replenishing the charge removed from or added to the output filter capacitors by a sudden load step. therefore, the amount of output soar when the load is removed is a function of the output voltage and induc- tor value. the minimum output capacitance required to prevent overshoot (v soar ) due to stored inductor ener- gy can be calculated as: where ph is the total number of active phases. when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. input capacitor selection the input capacitor must meet the ripple-current requirement (i rms ) imposed by the switching currents. the multiphase controllers operate out-of-phase, which reduces the rms input current by dividing the input cur- rent between several staggered stages. for duty cycles less than 100%/ ph per phase, the i rms requirements can be determined by the following equation: where ph is the total number of out-of-phase switching regulators. the worst-case rms current requirement occurs when operating with v in = 2 ph v out . at this point, the above equation simplifies to i rms = 0.5 x i load / ph . for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to inrush surge currents, typical of systems with a mechanical switch or connector in series with the input. if the max8707 is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. in either configuration, choose an input capacitor that exhibits less than 10 c temperature rise at the rms input current for optimal circuit longevity. setting voltage positioning voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the out- put capacitance and processor s power-dissipation requirements. the controller uses two transconduc- tance amplifiers to set the transient and dc output volt- age droop ( figure 2). the transient-compensation (trc) amplifier determines how quickly the max8707 responds to the load transient. the slower voltage-posi- tioning (vps) amplifier adjusts the steady-state regula- tion voltage as a function of the load. this adjustability allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller current- sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r vps ) between vps and fbs to set the dc steady-state droop (load line) based on the required dc voltage-positioning slope (r droop ): where the current-sense resistance (r sense ) depends on the current-sense method, and the voltage-position- ing amplifier s transconductance (g m(vps) ) is typically 200s as defined in the electrical characteristics table . when the max8707 crs sensing is enabled, r sense is defined as the accurate crs current-sense resistance: r sense =r crs when crs sensing is enabled. when the max8707 crs sensing is disabled, the con- troller sums together the input signals of the current- sense inputs (csp_, csn_). these inputs typically use the inductors dc resistance (r dcr ) to sense the cur- rent, so r sense is defined as the average of the effec- tive cs current-sense resistances (see the current sense section): r sense = r dcr when crs sensing is disabled. when the inductors dcr (r dcr ) is used as the cur- rent-sense elements (for lossless sensing), r vps should include an ntc thermistor to minimize the temperature dependence of the voltage-positioning slope. to avoid output-voltage errors caused by the voltage- positioning current, a second transconductance ampli- fier generates an equivalent current on the fbs input. accurate max8707 crs sensing is disabled by con- necting crsp to v cc . r r rg vps droop sense m vps = () i i v vv v rms load ph in ph out in ph out = ? ? ? ? ? ? ? ? () c il vv out load max ph out soar () () ? 2 2
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 33 disable voltage positioning by shorting vps directly to fbs. transient droop connect a resistor (r trc ) between trc and ref to set the transient droop (r droop(ac) ) based on the voltage- positioning requirements. trc allows the controller to quickly respond to load transients, but it does not affect the dc steady-state droop. choose r trc based on the equation: where r cs is the current-sense element connected from csp_ to csn_ (which is typically the inductor s effective dcr: r cs = l / r eq c sense ), r trans is the current- sense amplifier gain divided by the transient amplifier s transconductance as defined in the electrical character- istics table , and r droop(ac) is typically 80% of the dc voltage-positioning slope to minimize the transient sag voltage. the trc resistance also sets the small-signal loop gain, so a maximum r trc value is required for stability, even if voltage positioning is not used (vps = fbs). v ripple r trc < (r trans r sense ? i l ) / 3 trc is high impedance in shutdown. applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by stability requirements, not the minimum off-time (t off(min) ). the max8707 does not include slope compensation, so the controller becomes unsta- ble with duty cycles greater than 50% per phase: v in(min) 2v out(max) however, the controller may briefly operate with duty cycles over 50% during heavy load transients. maximum input voltage the max8707 controller and driver has a minimum on- time, which determines the maximum input operating voltage that maintains the selected switching frequen- cy. with higher input voltages, each pulse delivers more energy than the output is sourcing to the load. at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse resulting in pulse- skipping operation regardless of the operating mode selected by skip. this allows the controller to maintain regulation above the maximum input voltage, but forces the controller to effectively operate with a lower switch- ing frequency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f sw is the switching frequency per phase select- ed by osc, and t on(min) is 110ns plus the driver s turn-off delay (pwm low to lx low) minus the driver s turn-on delay (pwm high to lx high). for the best high- voltage performance, use the slowest switching-fre- quency setting (200khz per phase, osc = gnd). pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention ( figure 9). if possible, mount all of the power compo- nents on the top side of the board with their ground ter- minals flush against one another. follow these guidelines for good pc board layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 2) connect all analog grounds to a separate solid cop- per plane, which connects to the gnd pin of the controller. this includes the v cc bypass capacitor, ref and gnds bypass capacitors, compensation (ccv, trc) components, and the resistive dividers connected to i lim(ave) , susv, and ofs. 3) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pc boards (2oz vs. 1oz) can enhance full- load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. 4) connections for current limiting (csp_, csn_) and voltage positioning (crsp, crsn) must be made using kelvin-sense connections to guarantee the current-sense accuracy. 5) route high-speed switching nodes and driver traces away from sensitive analog areas (ref, ccv, trc, vps, etc.). make all pin-strap control input connec- tions ( shdn , skip, sus, osc) to analog ground or v cc rather than power ground or v dd . 6) keep the drivers close to the mosfet, with the gate-drive traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. vv ft in skip out sw on min () () = ? ? ? ? ? ? 1 r rr r trc trans cs ph droop ac = ()
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 34 ______________________________________________________________________________________ output cpu input kelvin sense vias under the sense resistor (refer to the evaluation kit) c out c in c in c in c in c in c in c out c out c out c out c out r sense connect gnd and pgnd to the controller at one point only as shown connect the exposed pad to analog gnd place controller on backside when possible, using the ground plane to shield the ic from emi inductor inductor inductor inductor power ground power ground power ground (inner layer) analog ground (inner layer) figure 9. pc board layout example
this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot- through currents. 7) when trade-offs in trace lengths must be made, it s preferable to allow the inductor charging path to be made longer than the discharge path. for example, it s better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. layout procedure 1) place the power components first, with ground termi- nals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connec- tions on the top layer with wide, copper-filled areas. 2) mount the driver ic adjacent to the low-side mosfets. the dl gate traces must be short and wide (50mils to 100mils wide if the mosfet is 1in from the driver ic). 3) group the gate-drive components (bst diodes and capacitors, v dd bypass capacitor) together near the driver ic. 4) make the dc-dc controller ground connections as shown in the standard application circuits . this dia- gram can be viewed as having three separate ground planes: input/output ground, where all the high-power components go; the power ground plane, where the pgnd pin, v dd bypass capacitor, and driver ic ground connection go; and the con- troller s analog ground plane, where sensitive ana- log components, the master s gnd pin, and the v cc bypass capacitor go. the controller s analog ground plane (gnd) must meet the power ground plane (pgnd) only at a single point directly beneath the ic. the power ground plane should connect to the high-power output ground with a short, thick metal trace from pgnd to the source of the low-side mosfets (the middle of the star ground). 5) connect the output power planes (v core and sys- tem ground planes) directly to the output-filter- capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter cir- cuit as close to the cpu as is practical. max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies ______________________________________________________________________________________ 35
chip information transistor count: 9011 process: bicmos max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies 36 ______________________________________________________________________________________ thin qfn 6mm x 6mm csp4 csn4 gnd ccv gnds vps pwm1 d0 d1 d2 d3 d4 n.c. ofs ref ilim(ave) v cc time osc pgnd vrok sus susv trc ilim(pk) fbs csp3 csn3 csp2 csn2 csp1 csn1 crsp crsn pwm2 pwm3 pwm4 13 14 15 16 17 18 19 20 10 9 8 7 6 5 4 3 2 1 31 32 33 34 35 36 21 22 23 24 25 26 27 28 29 30 40 39 38 37 12 11 skip shdn drskp top view max8707 pin configuration
max8707 multiphase, fixed-frequency controller for amd hammer cpu core power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 37 ? 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin 6x6x0.8 .eps e e l l a1 a2 a e/2 e d/2 d e2/2 e2 (ne-1) x e (nd-1) x e e d2/2 d2 b k k l c l c l c l c l e 1 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm l1 l e 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. nd and ne refer to the number of terminals on each d and e side respectively. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 9. drawing conforms to jedec mo220, except for 0.4mm lead pitch package t4866-1. 7. depopulation is possible in a symmetrical fashion. 3. n is the total number of terminals. 2. all dimensions are in millimeters. angles are in degrees. 1. dimensioning & tolerancing conform to asme y14.5m-1994. notes: 10. warpage shall not exceed 0.10 mm. e 2 2 21-0141 package outline 36, 40, 48l thin qfn, 6x6x0.8mm

▲Up To Search▲

Price & Availability of MAX8707ETL

	To Download MAX8707ETL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .